NASA's Next-Generation AI Processor Passes Early Testing

By Matthew Williams - May 25, 2026 08:28 PM UTC | Space Exploration
Small enough to fit in the palm of a hand, NASA’s High Performance Spaceflight Computing processor packs the power of a full system-on-a-chip. Credit: NASA/JPL-Caltech
Small enough to fit in the palm of a hand, NASA’s High Performance Spaceflight Computing processor packs the power of a full system-on-a-chip. Credit: NASA/JPL-Caltech

As space exploration takes spacecraft and crews farther and farther from Earth, the need for systems that can operate with minimal (or zero) human oversight increases. This is needed in part because of the distances involved, where astronauts on the Moon and Mars will be subject to communication delays that make it harder to send and receive reports and data promptly. At the same time, autonomous systems have the potential to accelerate the rate of scientific returns through faster data analysis.

At the same time, processors need to be hardened to withstand the harsh environment of space, including extreme temperatures and high levels of radiation. To address this need, NASA's Game Changing Development (GCD) program entered into a commercial partnership to develop the High Performance Spaceflight Computing (HPSC) system. This revolutionary chip will give spacecraft the processing capabilities to think for themselves, and just completed its first round of environmental tests.

Building computers that can handle the challenges of spaceflight requires processors that deliver high-quality data while also withstanding the harsh conditions of space (extreme temperature variations and radiation). Traditionally, NASA has relied on chips developed in previous decades, which were designed to be hardy and reliable. But given the current rate at which missions accumulate data, upgraded chips are needed to process and analyze it faster and more efficiently.

NASA's HPSC shown with its exterior casing attached. Credit: NASA/JPL-Caltech/Ryan Lannom *NASA's HPSC shown with its exterior casing attached. Credit: NASA/JPL-Caltech/Ryan Lannom*

This has led NASA and the Arizona-based tech company Microchip Technology Inc. to create HPSC, a radiation-hardened high-performance processor capable of delivering 100 times the computing capability of current systems. The project is managed by the Space Technology Mission Directorate (STMD) based at NASA Langley. NASA's Jet Propulsion Laboratory (JPL) developed mission requirements, funded industry studies, and selected Microchip Technology as its commercial partner, which funded its own research and development.

The HPSC processor is an example of a system-on-a-chip (SoC), a compact integrated circuit typically found in smartphones and tablets that integrates all essential elements of a computing system into a single microchip. This includes central processing units (CPUs, computational offloads, advanced networking units, memory, and input/output interfaces.

However, only the SoCs JPL is testing are built to survive for years while operating millions or even billions of km from Earth and repair facilities. “Building on the legacy of previous space processors, this new multicore system is fault-tolerant, flexible, and extremely high-performing,” said Eugene Schwanbeck, program element manager in NASA’s GCD program. “NASA’s commitment to advancing spaceflight computing is a triumph of technical achievement and collaboration.”

In addition to computing power, the chips will provide high-performance AI dataflow processing with scalable vector computing capabilities. In addition, the HPSC is designed to be adaptable in terms of power consumption and computing performance, so functions can be turned off when not in use or put into lower-power modes. This ability means the HPSC processor can be used for missions with varying power requirements, improving power efficiency since electrical power is such a vital resource in space.

Animation of a lunar rover operating autonomously using NASA's HPSC chip. Credit: NASA/JPL-Caltech *Animation of a lunar rover operating autonomously using NASA's HPSC chip. Credit: NASA/JPL-Caltech*

To ensure these chips can handle spaceflight, technicians at NASA’s Jet Propulsion Laboratory have been conducting various tests that replicate the challenges they will face, such as electromagnetic radiation and extreme temperatures. High-energy particles from the Sun (solar wind) and cosmic rays can cause errors, and extreme cold can cause batteries to shut down, both of which will send a spacecraft into “safe mode." Said Jim Butler, High Performance Space Computing project manager at JPL:

We are putting these new chips through the wringer by carrying out radiation, thermal, and shock tests while also evaluating their performance through a rigorous functional test campaign. To simulate real-world performance, we are using high-fidelity landing scenarios from real NASA missions that would typically require power-intensive hardware to process huge volumes of landing-sensor data. This is an exciting time for us to be working on hardware that will enable NASA’s next giant leaps.

Testing began in February at JPL and will continue for several months, and the results have been promising so far. From what JPL engineers have seen, the processor is performing at 500 times the performance of the radiation-hardened chips currently in use. Once certified for spaceflight, NASA will incorporate the chip into the computing hardware of future orbiters, rovers, habitats, and deep space missions.

In addition to space, the HPSC chip has applications in Earth-based industries such as aviation and automotive manufacturing, for which Microchip Technology is currently adapting it. The HPSC's versatility is in keeping with NASA's history of developing cutting-edge technology while also providing "spinoffs" benefits for numerous fields on Earth.

Further Reading: NASA

Matthew Williams

Matthew Williams

Matt Williams is a space journalist, science communicator, and author with several published titles and studies. His work is featured in The Ross 248 Project and Interstellar Travel edited by NASA alumni Les Johnson and Ken Roy. He also hosts the podcast series Stories from Space at ITSP Magazine. He lives in beautiful British Columbia with his wife and family. For more information, check out his website.